The present invention relates to a semiconductor device and a method of manufacturing the same. Particularly, the present invention is concerned with a technique effectively applicable to a method (MAP: Matrix Array Packaging method) which involves block-molding a main surface side of a wiring board (substrate) with an insulating resin to cover the main surface side with a seal member, or a package, and thereafter dividing the mutually superimposed substrate and seal member longitudinally and transversely to afford plural semiconductor devices.
In semiconductor devices incorporated into small-sized electronic devices such as portable telephones, portable information processing terminal devices, and portable personal computers, it is required to reduce the thickness and size and attain a multi-pin structure. As package forms of semiconductor devices adapted for such a multi-function and high density configuration there are known such package structures as BGA (Ball Grid Array) and CSP (Chip Size Package).
As a method for fabricating such BGA or CSP there is known a method comprising providing a wiring substrate, then mounting a semiconductor chip (semiconductor element) at a predetermined position on a main surface of the wiring substrate, connecting electrodes on the semiconductor chip and wiring lines on the main surface of the wiring substrate with each other through conductive wires, then covering the main surface side of the wiring substrate with a sealing resin, and forming salient electrodes (bump electrodes) on a back surface of the wiring substrate which electrodes are connected to wiring lines.
In connection with a semiconductor device manufacturing method having a step of fixing a semiconductor chip onto a wiring substrate with use of an adhesive, there has been posed a problem that the adhesive flows out and contaminates electrodes formed on the wiring substrate, making an electrical connection with the electrodes difficult.
FIGS. 34 and 35 each illustrate a relation between a wiring board (substrate) 1 and a semiconductor chip 3 fixed onto the wiring substrate through an adhesive 2, in a conventional structure (a first conventional product) which the present inventors had studied prior to the present invention. Insulating films (solder resists) 4 and 5 are formed on a main surface (upper surface) and a back surface, respectively, of the wiring substrate 1 in accordance with predetermined patterns, and the semiconductor chip 3 is fixed through the adhesive 2 onto the insulating film 4 formed on the main surface of the wiring substrate 1.
Electrodes (not shown) formed on the semiconductor chip and electrodes 7b formed on the main surface of the wiring substrate 1 are interconnected through conductive wires. For this connection it is necessary that the electrodes 7b be exposed to the main surface of the wiring substrate 1. As a structure for exposing the electrodes 7b there generally is adopted such a structure as shown in FIG. 34 or 35. In the structure of FIG. 34, the insulating film 4 on the main surface of the wiring substrate 1 is removed by a predetermined width to form an opening groove 9, in which the electrodes 7b are positioned. In the structure of FIG. 35, insulating film portions which cover the electrodes 7b are removed, allowing the electrodes 7b to be exposed. As the adhesive 2 there is used an epoxy resin (paste).
In such structures, a sufficient distance between a chip end and the electrodes 7b on the wiring substrate 1 is ensured to prevent contamination of the electrodes 7b even if the adhesive 2 which fixes the semiconductor chip 3 onto the wiring substrate flows out from the chip end, as shown in FIGS. 34 and 35. As an example, in the structure of FIG. 34 having the opening groove 9, the distance a between a chip end and an edge of the opening groove 9 is set as long as 0.50 mm, while in the structure of FIG. 35, the distance b between a chip end and an edge of the insulating film 5 is set as long as 0.525 mm. In both structures, the distance m between the chip end and an end of the wiring substrate 1 is 1.10 mm.
The thickness, f, of the wiring substrate 1 is about 0.210 mm, the thickness, h, of the insulating film 4 is about 0.30 mm, the thickness, g, of the insulating film 5 is about 0.30 mm, the thickness, j, of the semiconductor chip 3 is about 0.22 mm, and the thickness, k, of the adhesive portion where the semiconductor chip 3 is bonded to the wiring substrate 1 is about 0.025 mm.
As another structure for preventing the contamination of electrodes on a substrate caused by flowing out of an adhesive there is known such a structure as shown in FIG. 36. FIG. 36 illustrates a second conventional product which the present inventors had studied prior to the present invention. In this second conventional product, for preventing the contamination of electrodes 7b on a main surface of a wiring substrate 1 caused by an adhesive 2, an insulating film 4a is laminated onto and along an inner periphery edge of the opening groove 9 formed in an insulating film 4 on the main surface of the wiring substrate 1 and is used as a dam for preventing the adhesive 2 from flowing into the groove 9.
Further, having made a private search of prior art literatures from the standpoint of preventing the contamination of electrodes on a main surface of a substrate caused by protrusion of a chip bonding adhesive, the following prior art literatures were extracted: Japanese Unexamined Patent Publication Nos. Hei 8(1996)-181166, Hei 7(1995)-45641, Hei 8(1996)-167678, and 2000-286271.
On the other hand, as a semiconductor device manufacturing method there is known a block molding method. The block molding method comprises mounting semiconductor chips respectively on plural product forming areas of a wiring substrate, then placing the wiring substrate within a molding die having a large cavity which covers the plural product forming areas, then block-molding the plural product forming areas with a sealing resin, and subsequently cutting both seal member and wiring substrate together into individual pieces by a dicing device. The block molding method is described, for example, in Japanese Published Unexamined Patent Application No. 2000-12578 (U.S. Pat. No. 6,200,121).
In the block molding method, after sealing with a sealing resin, both seal member and substrate are cut into individual pieces by a dicing device. As a result of being cut by the dicing device, the seal member is cut vertically and is hence free of any tapered portion. Moreover, since both seal member and substrate are cut simultaneously, the substrate is not required to have an allowance for cut. Consequently, it is possible to shorten the distance between a chip end and a substrate end and hence possible to reduce the size of product (semiconductor device). For example, the distance between a chip end and a substrate end is 800 μm in an embodiment.